How to use design verifier with incompatible simulink models?

2 次查看(过去 30 天)
I have a Simulink model with an integrator block that cannot be stubbed while running the design verifier, rendering the model incompatible with the design verifier. Is there a way to increase the coverage of such a model other than manually building test cases?
  1 个评论
Akshat Dalal
Akshat Dalal 2025-1-21
Hi Tushar,
You will have to write your own block replacement rules to handle the unsupported blocks for SLDV. Please refer the following documentations for more information:
Thanks

请先登录,再进行评论。

回答(0 个)

类别

Help CenterFile Exchange 中查找有关 Verification, Validation, and Test 的更多信息

Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!

Translated by