Problem in checking the D Flipflop Block, Simulink

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Ram Prasadh Narayanan 2016-9-6

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https://ww2.mathworks.cn/matlabcentral/answers/302061-problem-in-checking-the-d-flipflop-block-simulink

关闭： MATLAB Answer Bot 2021-8-20

Hi, I wanted to check the D Flipflop block in simulink. So I provided a pulse input and a clock to it. There is a 3rd input called the !CLR. It is mentioned in the page that * "On the positive (rising) edge of the clock signal, if the block is enabled (!CLR is greater than zero), the output Q is the same as the input D"*. I gave the inputs and I don't get the desired output that if the clock is high, the output follows the input and remains in the same state until next rising clock. The d flipflop block doesn't behave in this sense. I have attached an image here of. The 1st signal is the input 'D'. 2nd is the clock. 3rd is the output and 4th signal is the !CLR. Please point to me on where I am going wrong.