As the Readiness report states, you are using several functions not supported for HDL code generation. The VideoReader object accesses a disk file and reads the file into memory. This is not something that can be performed on an FPGA, which has no file system. Similarly, you are displaying the file via the movie function. This requires a display, which also is not available on an FPGA.
You need to ask yourself what it is that you are trying to do with the hardware, and what portion of your overall design can be placed onto an FPGA. A typical flow will have the testbench reading the input data stream, passing it to the hardware portion of the design, and finally displaying the resulting processed output data. The portion of the design converted to HDL is the video transform that sits in the middle.
My suggestion is to start with some of the simple HDL Coder Examples in the documentation to learn the tool flow and some of its capabilities. Once you are familiar with the basics of the tool, there are more advanced HDL Coder Image Processing examples that demonstrate some of the techniques necessary to efficiently handle and process a video stream.
