why the error is occuring while converting from simulink to vhdl?

Question

ramandeep kaur 2016-11-17

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https://ww2.mathworks.cn/matlabcentral/answers/312608-why-the-error-is-occuring-while-converting-from-simulink-to-vhdl

回答： Tim McBrayer 2016-11-17

i was converting simulink model to vhdl. and this error is showing up "Data-type 'Fix_16_14' is unsupported for HDL code generation. If Xilinx System Generator Subsystem is used, make sure it is not the top level subsystem for code generation." can you please help me out. thank you

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Answer 1

Tim McBrayer 2016-11-17

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https://ww2.mathworks.cn/matlabcentral/answers/312608-why-the-error-is-occuring-while-converting-from-simulink-to-vhdl#answer_243673

Are you using Xilinx System Generator, and if so, is it at the top of the design hierarchy? If so, you need to fix that, just like the message says.

If you are not using XSG, then you need to use MathWorks' fixpt specification for your data type. Instead of Fix_16_14, you should specify the data type as fixdt(1, 16, 14) for a signed type, or fixdt(0,16,14) for an unsigned type.