How to solve "For MATLAB Function block generation, structure inputs to the top-level design function are not supported"

Question

Bo Zhang 2016-11-21

0
链接

此问题的直接链接

https://ww2.mathworks.cn/matlabcentral/answers/313291-how-to-solve-for-matlab-function-block-generation-structure-inputs-to-the-top-level-design-functio

评论： Bo Zhang 2016-11-23

Hello, I come across a problem during using vision HDL coder. I coded as pixel-based processing, and try to stream the image frames. However, as for the control output, I just simply make it equal to ctrlIn. Below is my code, which differentiates the successive two frames:

function [pixOut,ctrlOut] = frame_difference(pixIn,ctrlIn,pixel_index)
persistent frame_buffer;
if isempty(frame_buffer)
   frame_buffer = zeros(307200,1);
end
last_time_value = frame_buffer(pixel_index);
frame_buffer(pixel_index) = pixIn;
difference = abs(pixIn - last_time_value);
if (difference > 12)
   pixvalue = 255; 
else
   pixvalue = 0; 
end
    pixOut = pixvalue;
    ctrlOut = ctrlIn;

And the testbench is the same as example. However, when I tried to convert the block to verilog, I encountered the error: For MATLAB Function block generation, structure inputs to the top-level design function are not supported. Actually, in the document (https://www.mathworks.com/help/hdlcoder/ug/variables-and-constants.html), the structures are said to be supported (I am not using Turnkey or IP generation ).

How can I solve this problem? Can I just simply omit the control signal for both input and output? Thanks very much!

4 个评论
显示 2更早的评论隐藏 2更早的评论

Walter Roberson 2016-11-22

Which MATLAB release are you using?

Bo Zhang 2016-11-23

Matlab 2016a

请先登录，再进行评论。

请先登录，再回答此问题。

Answer 1

Walter Roberson 2016-11-22

0
链接

此回答的直接链接

https://ww2.mathworks.cn/matlabcentral/answers/313291-how-to-solve-for-matlab-function-block-generation-structure-inputs-to-the-top-level-design-functio#answer_244277

This is not something that I have experience with, but the two questions that come to mind are:

is it necessary to embed this in a subsystem and generate for the subsystem?
can a structure cross the HDL boundary, or does it need to be serialized or broken out into distinct pins? There are constructs that can be used inside the HDL but which cannot cross the boundaries intact.