How to manually convert MATLAB code into Verilog code?

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Aniket Jangam
Aniket Jangam 2017-2-11
评论： Walter Roberson 2017-2-12
I read on forums but all the answers mention conversion using HDL Coder. Can anyone please tell me how to do the conversions manually or some reference book for the same. Thanks in advance.

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Bharath Venkataraman
编辑：Bharath Venkataraman 2017-2-11
Please take a look at the examples provided with HDL Coder - you can do HDL conversion from Simulink or MATLAB designs. Typical things you have to do for HDL code generation is to serialize (possibly do fixed point conversion) of your design. Link to Code examples
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Aniket Jangam
Aniket Jangam 2017-2-11
First of all thanks Bharath for the guidance. Also, could you please tell me the steps for conversion of the codes? What I guess is I will be writing some simple code using Floating point number in MATLAB and then rewrite that in Fixed point in MATLAB itself. Then further manually change it to Verilog HDL, write a testbench for the same and simulate it to verify. Is this the right way? Thanks again.
Bharath Venkataraman
Bharath Venkataraman 2017-2-11
Yes, you have the procedure correct.
  1. For example, if all you did was an adder of a value and it's previous value in a matrix, you could just start with add_out = add_in1(1:end-1) + add_in2(2:end); In this code, you could handle a whole frame of floating point samples at a time.
  2. Then you could put in serialization and get only one value into the function. In this case, you would need to put a delay block in Simulink and add the input of the delay to the output of the delay block. Gather data back and verify it is the same as last time.
  3. Next you add in fixed point. Use a data type conversion block in Simulink to model the fixed point data coming in (signed/unsigned, how many bits for the integer part, and how many for the exponent part). You can still use the delay and adder in the previous step, but you may want to see if the default fixed point setting for the adder block works or if you want to change it to some other fixed point. Again, verify that this matches your earlier result.
  4. You can now either generate Verilog for the design and the testbench directly using HDL Coder (make sure your design a subsystem), or you can write it by hand and save the data from Simulink into a file and use it as your testbench input. You can also generate the design and Testbench code and throw away the design, but use the Testbench.

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Walter Roberson
Walter Roberson 2017-2-11
You rewrite the MATLAB into C by hand, and then you use a C to HDL conversion tool; https://en.wikipedia.org/wiki/C_to_HDL
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Aniket Jangam
Aniket Jangam 2017-2-11
Thanks Walter for the answer. Well our professor said the code generated through such tools isn't efficient enough so I am thinking to avoid any tool an do the complete conversion manually. Could you please give me a simple code of conversion MATLAN-C-Verilog, here? So that i can refer it and make something accordingly. Thanks again!
Walter Roberson
Walter Roberson 2017-2-12
Although ARM was quite successful with hand design in the mid 1980s, you need to know a lot about synthesis and programming in order to do better than optimizing compilers.
Humans find it difficult to plan for concurrency. There is a field of study for concurrency planning with multiple resources (of possibly different classes) to find the best order to execute several tasks simultaneously. But you need to be thinking of that all of the time when you are planning HDL -- need to be worrying about doing as much as possible at the same time without exceeding heat or power budgets and making sure that any data transport lines are not in contention. Compilers do all of that automatically.
You can find some of the scheduling programs at https://www.mathworks.com/matlabcentral/fileexchange/?term=job+scheduling

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