Fpga-in-the-loop using IP core generation workflow with reference design?
显示 更早的评论
Hi,
I would like to generate a baseband processor IP using HDL coder and implement it on an FPGA connected to Simulink (in the loop). The goal is to allow easy configuration of IP parameters and inspection of performance metrics. One particular constraint is that the design within the FPGA has many other components, so at first my understanding is that I should adopt the "IP Core Generation" workflow within the HDL Coder Workflow advisor and adapt the current FPGA design with "blank" connections for the IP that I intend to generate, then use this design as a reference design. However, from what I read, I understood that the FPGA-in-the-loop functionality is only enabled for the "Generic ASIC/FPGA" or the "FPGA Turnkey" workflows, both which do not allow a reference design to be included.
Have I misunderstood it? What would be an advisable solution in this case, to allow Simulink connectivity to the FPGA and also integrate an IP generated by HDL coder with a reference design?
Thanks
采纳的回答
Tao Jia
2017-5-5
0 个投票
Hi Igor,
Currently the IP core generation workflow does not support FPGA-in-the-Loop.
If you want to communicate with the generated IP core on FPGA from MATLAB/Simulink, you can check out this one and see if it helps:
https://www.mathworks.com/help/hdlcoder/examples/ip-core-generation-workflow-without-an-embedded-arm-processor-xilinx-kintex-7-kc705.html
Tao
更多回答（1 个）
类别
在 帮助中心 和 File Exchange 中查找有关 Xilinx Zynq Platform 的更多信息
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!
Translated by 
