getting error while converting matlab code to verilog
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while converting matlab to verilog in hdl coder error getting testbench. ERROR : Error using eml_error (line 20) BIT must be integers between 1 and 9 for embedded.fi. i cannot even understand meaning of that error, can u figure it out
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Bharath Venkataraman
2017-5-17
编辑：Bharath Venkataraman
2017-5-17
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Do you have any bit manipulation code? In that case, one guess is that the index you are passing needs to be between 1 and 9, where as the value you are passing in is not between those values. Showing the code here may help debug it.
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