HDL coder Clocking Module

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shauk
shauk 2017-5-7
评论： shauk 2017-5-8
Hallo
Can any one explain me how the clocking module works when i am generating HDL code from a simulink model For example lets say i have 44.1 kHz input signal and then two interpolation filter one with 32 upsample and second with 8 upsample, so my output frequency is 11.2 MHz. How does simulink make sure that they all get the correct clock module?

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回答（1 个）

Bharath Venkataraman
Please take a look at the documentation for single and multiple clocking modes in HDL Coder.
  1 个评论
shauk
shauk 2017-5-8
hallo
thanks for the link, please correct me if i am wrong. So when creating a deign simulink already provides the clock bundle in the design which we can not see but is in the vhdl file. while doing the pin planning for the fpga do we need to put the clock enable as a input pin? and supply the clock enable value to the design using a clock module?

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