Can I perform FPGA in the Loop with SysGen for DSP without HDL Coder and Verifier ?

2017 6 9
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更新时间：2017 6 14
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Hi,
For my internship I have to implement FPGA in the Loop in Matlab. I have a licence for System Generator for DSP but it's not possible to have a license for HDL Coder or HDL Verifier. If I have already my VHDL code, it's possible to perform FIL with only SysGen for DSP ?
Thank you in advance

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