Large dsp.HDLFFT result discrepancy with floating point simulation.

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imcuser1
imcuser1 2017-9-15
回答： Alireza 2017-9-18
Hi everybody,
I am designing a 4K FFT with 4-bit signed inputs. The simulated result differ from floating point simulation by a large percentage, say 20% and more. The stem plot is difference while the blue and red are fixed and floating point values.
What can I do to improve it?
c = 2*randi([0,1], 1, 1023)-1;
c2 = reshape([c;c;c;c], 4092, 1);
c1 = complex([c2', zeros(1,4)], [c2', zeros(1,4)]);
y_fixed = real(c1); N = 4096;
Yf = zeros(1,3*N);
validOut = false(1,3*N);
for loop = 1:1:3*N
if (mod(loop, N) == 0)
i = N;
else
i = mod(loop, N);
end
tmp1 = sfi(y_fixed(i), 4, 0);
tmp = (loop <= N);
[Yf(loop),validOut(loop)] = HDLFFT4K(tmp1 ,tmp);
if (mod(loop, 256) == 0) % debug
loop
end
end
Yr = Yf(validOut == 1);
fc0 = bitrevorder(Yr);
%{ Debug }%
fc2 = fft(real(c1));
dd = fc0 - fc2;
figure;
subplot(2,1,1); plot(real(fc2), 'r'); hold on; plot(real(fc0), 'b'); stem(real(dd));
subplot(2,1,2); plot(imag(fc2), 'r'); hold on; plot(imag(fc0), 'b'); stem(real(dd));
function [yOut,validOut] = HDLFFT4K(yIn,validIn)
%HDLFFT128
% Processes one sample of FFT data using the dsp.HDLFFT System object(TM)
% yIn is a fixed-point scalar or column vector.
% validIn is a logical scalar value.
% You can generate HDL code from this function.
persistent fft4k;
if isempty(fft4k)
fft4k = dsp.HDLFFT('FFTLength', 4096, 'RoundingMethod', 'Nearest');
end
% fft4k.release();
[yOut,validOut] = fft4k(yIn,validIn);
end

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回答（2 个）

Alireza
Alireza 2017-9-15
You need to have more bits, specially fractional bits to get better result. Your fixed point is 4 bits with 0 fractional bits and it is hard to compare it with floating point. With your 4 bits and zero fractional bits the abs(max(dd)) = 234. If you change your fixed-point data type to sfi(y_fied(I, 4, 2)) with two fractional bits you will get abs(max(dd)) = 63. With sfi(y_fied(I, 16, 14)), the maximum error will be abs(max(dd)) = 9e-3;
  1 个评论
imcuser1
imcuser1 2017-9-18
编辑：imcuser1 2017-9-18
Thank you Alireza. Reading the RTL I see the twiddle factor is 4 bit in case of a sfi(4,0). Any method to make twiddle factors more precise while keeping the adc input fixed at 4 bit signed integer?

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Alireza
Alireza 2017-9-18
Currently there is no way to select twiddle factors wordlength. We should note that the optimal twiddle factor wordlength in FFT is the same as input data wordlength, and it is what dsp.HDLFFT selects. Smaller twiddle factor wordlength causes precision loss, and bigger wordlength will not increase accuracy since the input data doesn't have that much of accuracy. At the same time bigger twiddle factors' wordlength requires more logic in FPGA. If you have only 4 bits data coming from ADC, cast it to bigger wordlength depending on the required FFT precision, for example sfi(8,6). This will increase in FPGA resource a little bit, but it provides the precision that you require.

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