Issue with generated library blocks

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Faris Shahin
Faris Shahin 2017-10-26
回答： Neil MacEwen 2017-10-26
I've been stuck with a problem for few days now. I've made some modification to the "Targeting HDL Optimized QPSK Transmitter Using Analog Devices AD9361/AD9364" example in MATLAB to modulate the signal using 4-QAM instead of QPSK. When running the simulation of the system, the constellation at the receiver shows correct results. I went through all of the "HDL Workflow Advisor" steps successfully. However, when I construct the transmitter system using the blocks from the library created during the "HDL Workflow Advisor", I don't get any correct results. The simulation is run in "External" mode. The next two screenshots show the transmitter circuit and the constellation of the received signal. I should note that the constellation "After Timing" keeps jumping between the 4 locations where a correct 4-QAM constellation should be.
However, when I use the exact same blocks for transmission with the "ZedBoard and FMCOMMS2/3/4 Transmitter" block which comes with the communication systems toolbox, the transmitter works without any problem. Of course, I've unchecked "Bypass user logic" option for the transmitter block. The next two screenshots show the transmitter circuit and the constellation of the received signal.
For me, it's important for the first system to work because in the near future I will need to send and/or receive some control signals to/from the FPGA. Is there any explanation why the first system doesn't work? Do I need to set some options before running the simulation?

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Neil MacEwen
Neil MacEwen 2017-10-26
Hi Faris,
You are using the support package in two different ways in your description above.
In the second case, you are sending data from your host PC to the board, which is passed to the FPGA, runs through your QAM transmitter and is transmitted. In this case, Simulink is not running in real time and will send data as fast as it can to the board, which is probably fast enough to feed your transmitter.
When you use the blocks generated by the HW/SW co-design workflow, and run the model in External Mode, as you do in your first case, you are generating code from your Simulink model to run on the ARM processor. In this case the ARM will be running according to a schedule configured from your model settings, including the absolute rates in the model. Please see the System Timing section in the documentation. Essentially, you will need to set up your Simulink model so that it is feeding enough data to the transmitter. I suspect if you monitor the underflow port you will see that you are experiencing underflows. There is some more documentation on configuring your software interface model here.
Hopefully this helps.
Neil

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