During HDL Code setup, there is is a check to enable "Balanced Delays". Checking this option causes modifications in the generated code that may cause small, but not negligible, differences in simulation behavior. If you are seeing unexpected numerical differences in this scenario, make sure that this option is left unchecked.
You may see numerical differences in Simulink simulation vs FPGA simulation when using the following workflow:
1) You have a model built with single/double types
2) You convert this model to fixed-point using a fixed point tool
3) You copy the converted fixed-point model into another model, and generate HDL code from this new model
4) You see numerical differences when viewing the FPGA simulation
