when using Design Error Detection and generate test, Simulink Design Verifier has exceeded the maximum processing time

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huan xu
huan xu 2018-6-4
评论： huan xu 2018-6-6
when using Design Error Detection and generate test, Simulink Design Verifier has exceeded the maximum processing time,even if using the exsample

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Rishabh Rathore
Rishabh Rathore 2018-6-4
编辑：Rishabh Rathore 2018-6-4
One of the reasons for this could be that the 'maximum analysis time' in configuration parameter box is very small.
You can increase the 'maximum processing time' yourself.
In 'Configuration Parameters', select 'Design Verifier' from left panel and then in the 'Maximum analysis time' field, specify an appropriate time in seconds.
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huan xu
huan xu 2018-6-4
Now I using the example mode 'sldvdemo_fuelsys_logic' in 2016b to generate test mode ,it can not process after the 119th object, and no matter what the example mode or our own mode, I hope I can found the reason why it can not be process OK, how to check and modify.

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