how to simulate FFT HDL optimized?
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I created a simulink project containing "FFT HDL optimized block" and I converted it to HDL code by using Hdl coder.Then, I created testbench for it by using the option of "generate testbench" at Simulink. However, when I simulated the testbench, I encountered a problem at simulation.Simulation results are correct between 480 ns and 560 ns(I started to take data out from 480 ns because of latency of the FFT block).From 560 ns, the simulation started to give error according to expected data out value.How can I solve the problem? FFT Length of the Block=16 Clock Time=10 ns
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Alireza
2018-6-28
Hi, I could reproduce the failure in R2015a. But it is not reproducible is R2016a. It seems that the bug is fixed in R2016a release. Can you use/upgrade to R2016a and try your model Thanks Ali
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Alireza
2018-6-28
Hi, I believe you are using R2014a. If you provide the input data type, I can check if it is fixed in later versions. I recommend to use R2016a version or later. We made a big performance improvement to the block at that release and added frame support.
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