HDL workflow Advisor image
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I will use the HDL workflow to do image processing on the FPGA.
How do I input the image will not be a bunch of interfaces?
My image is 2D, how does the test bench code describe it?
回答（2 个）
Bharath Venkataraman
2018-7-2
0 个投票
This Vision HDL Toolbox page shows the capabilities provided for image processing on an FPGA. If you have the product, try doc visionhdl and look at the examples.
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Eric Cigan
2023-12-18
Please note that starting with the 24a general release, the features of the Xilinx Zynq Support from Vision HDL Toolbox will be available thorugh Xilinx Zynq SoC Support from SoC Blockset.
Eric Cigan
2023-12-18
0 个投票
Please note that starting with the 24a general release, the features of the Xilinx Zynq Support from Vision HDL Toolbox will be available thorugh Xilinx Zynq SoC Support from SoC Blockset.
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2023-12-18
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