"Data-type 'Fix_16_13' is unsupported for HDL code generation "

2012 6 13
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更新时间：2025 2 2
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I am trying to translate my Simulink design to Verilog code from HDL work flow advisor but i get the following error "Data-type 'Fix_16_13' is unsupported for HDL code generation " can you please help me out in this. I am using CORDIC SINCOS core to generate sine wave its output is of Fix_16_13 and workflow advisor is giving error on this output.

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回答（1 个）

Tim McBrayer
Tim McBrayer 2012-6-13

1 个投票

You need to find where you have specified "Fix_16_13" and correct the syntax. The string "Fix_16_13" is not a valid Simulink data type specification. If this string is intended to be a Simulink data type string, it should be fixdt(0,16,13) if unsigned, and fixdt(1,16,13) if the type is a signed type.

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Hamid
Hamid 2012-6-14
But i am using Xilinx Blockset Of Cordic SinCos and its output is intended to be Fix_16_13. Can you please tell me how can i change that to your suggested one in the block. Because there i only get to enter the input width 16 and binary point position 13. The output is predefined by the block itself.
姚辉
姚辉 2025-2-2
i met this question too,i also dont know how to solve

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Hamid
Hamid
2012-6-13

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姚辉
姚辉
2025-2-2

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