Typically, the speedgoat_IO333_06_all_io FPGA bitstream is for system testing purposes only. You might have a Custom Implementation.
The documentation includes the base pin mapping: https://www.speedgoat.com/help/page/io_main/refentry_io33x_6_pin_mapping
The digital channels (TTL) are listed as "FPGA Code Module functionality" because those channels would be configured with specific Code Modules in a Custom Implementation. In the case of the speedgoat_IO333_06_all_io FPGA bitstrea, pin 2-9, 36-38, and 41-41 correspond to digital I/O channel 1 to 13.
The analog I/O part cannot be configured with a Custom Implementation, so it is fixed.
For the analog inputs, in the A/D read block you can enable channels 1 to 16, by entering a vector. E.g. if you want to use analog input channels 1, 2, 3, 4 -> Channel vector: [1, 2, 3, 4]. Same applies for the analog output channels and the D/A write block.
To minimize the I/O latency, I recommend enabling only the channels that you effectively need. Also, by preference use consecutive channels.
