Signal is not properly sampling at the rising edge of clock.

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Sarfaraz Ahmed
Sarfaraz Ahmed 2018-10-7
编辑： Sarfaraz Ahmed 2018-10-7
Hi. I am sampling my input signal of frequency 50hz at the rising edge of clock and I am using simulatin time to sample my input. I am using simulation time because I have to introduce some delay later on clock.but it sample every time at zero. I am attaching my simulink model plus my sampler code below. The sampler block is inside of triggered subsystem. It seems it does not sample properly. Please help me in that model so I can solve this problem. Also can I use "pulstran" function instead of ideal clock ? If it does not work.
function Vin = sample(ip) coder.extrinsic('stem'); coder.extrinsic('get_param') persistent x1;
if isempty(x1) % Initialization x1=0; end
f=50; % input signal frequency sim_t=get_param('check','SimulationTime')
x1=sin(2*pi*f*sim_t);
stem(sim_t,x1); % plotting discrete samples on the input signal1
Vin=x1;
Thanks

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