HDL Coder Signed Inputs/Outputs

2019 1 28
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更新时间：2019 1 28
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I have a simple funtion to test the HDL Coder.
It is as follows:
function [sumnumn, diffnum, prodnum, quotnum] = asmd2num(a, b)
sumnum = a + b;
diffnum = a - b;
prodnum = a * b;
quotnum = a / b;
end
For the Clocks & Ports tab I have Synchronous,
Inpud data type = signed/unsigned
Output data type = signed/unsigned
Optimzations: Register Outputs
The issue is that the HDL output is always producing unsigned outputs.
How does one get SIGNED outputs?
And preferably SIGNED inputs?
Thanks

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 采纳的回答

Paul Sand
Paul Sand 2019-1-28

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It appears the whether one gets signed or unsigned is determined by the values in the test bench.

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