HDL Coder disable Clock Enable output port

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Michael Felger
Michael Felger 2019-2-27
回答： Bharath Venkataraman 2019-2-28
How can I disable the Clock Enable output port in generated VDHL-Code?
I can specify the name In HDL Code Generation -> Global Settings -> Ports -> Clock enable output port (default ce_out). But there is no checkbox to disable the output port.
The documentation says "A clock enable output is generated when the design requires one."
What is the condition for "when the design requires one"?

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采纳的回答

Bharath Venkataraman
There is not a separate option - it is assumed that a requirement of a clock enable on the input would mean one is desired on the output.

更多回答（1 个）

Bharath Venkataraman
You can use the option Minimize Clock Enables to remove the clock enable port. The clock enable typically cannot be removed for multi-rate designs.
HDL Code Generation -> Global Settings -> Ports -> Minimize clock enables (check this box).
  1 个评论
Michael Felger
Michael Felger 2019-2-28
I don't want to remove the clock enable INPUT port, only the clock enable OUTPUT port.
Activating the Minimize Clock Enables removes both.
Is there no option to remove the Clock Enable output port seperately?

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