Simulink Design Verifier Expected Output missing

Question

Nipurn Gulgulia 2019-3-18

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https://ww2.mathworks.cn/matlabcentral/answers/450646-simulink-design-verifier-expected-output-missing

评论： Shishir Dwivedi 2019-3-25

I am trying to generate Test cases using SLDV in Matlab2017a. I checked "Include Expected Output Value" under result section of Design Verifier. But still in .mat file and HTML report i am not able see any expected output. Is there any conition for output port/Signal or any other settings which needs to generate Expected Output result.

Is there anyone who can help me with it ?

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Answer 1

Pat Canny 2019-3-18

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https://ww2.mathworks.cn/matlabcentral/answers/450646-simulink-design-verifier-expected-output-missing#answer_365928

You should see the expected outputs in the sldvData.TestCases.expectedOutput field (from the .mat file). It should be an array of cell arrays.

In the report, you should see an Expected Output section for each Test Case generated.

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Nipurn Gulgulia 2019-3-22

I checked and its not there.

Is there any other thing need to check other than "Include Expected Output Value" under result section of Design Verifier.

Shishir Dwivedi 2019-3-25

Hi Nipurn,

Is the model having unconnected outports?
Are there any model references used in the main model & if yes then are the referenced models have SaveFormat = Dataset?. Change the save format to "Array" or "Structure with time" and see if you are able to get expected outputs.

Best Regards,

Shishir.

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