Communication Speed of "FPGA in the loop" in different communication ways?

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Liangmao Jiang 2019-4-3

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https://ww2.mathworks.cn/matlabcentral/answers/454144-communication-speed-of-fpga-in-the-loop-in-different-communication-ways

回答： Dave Gutierrez 2019-4-4

采纳的回答： Dave Gutierrez

I'm using "FPGA in the loop" with xilinx zc706 board. The only supported communication way is jtag. if I want run my code faster,should I buy a new board with eth support or pcie support? As we all know ,JTAG is slow ,ETH and PCIe is faster. Does MathWork's "FPGA in the loop" framework support to full the phy interface speed?

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Dave Gutierrez 2019-4-4

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-should I buy a new board with eth support or pcie support?

yes. FIL supports PCIe and Ethernet. The supported hardware for Xilinx:

https://www.mathworks.com/help/supportpkg/xilinxfpgaboards/ug/xilinx-fpga-board-support-from-hdl-verifier.html

You can also create a custom board definition file:

https://www.mathworks.com/help/hdlverifier/custom-fpga-board-definition.html

- Does MathWork's "FPGA in the loop" framework support to full the phy interface speed?

Depending on the PHY interface we support different speeds, please refer to the table in the link below:

https://www.mathworks.com/help/hdlverifier/ug/what-is-fpga-board-customization.html?searchHighlight=%22Ethernet%20PHY%20Interface%22&s_tid=doc_srchtitle#btmi8jh-8

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