importhdl vector index operation

Question

Stefano Buccelli 2019-6-5

0
链接

此问题的直接链接

https://ww2.mathworks.cn/matlabcentral/answers/465705-importhdl-vector-index-operation

编辑： Kiran Kintali 2020-10-19

Hi,

I'm trying to import this verilog "toy code" but I'm getting an error. (note: this code is just to test the import functionality)

module reduced (
    input wire                      clk,
    input wire                      reset,
    output wire [15           :0]   status
   );
    reg [6:0]  output_read_addr=0;        // the address at which we will read resulting samples
    reg [15:0]  output_read_data;        // the data that has been retrieved from memory
    reg [15:0]  output_storage[0:127];   // this memory is used to store data from the computing algorithm
    always @(posedge clk) begin
        output_read_data    <= output_storage[output_read_addr];
    end
endmodule