Hi
I have been using the 'dpigen' functionality to generate DPI shared-objects of matlab models which I use in my SystemVerilog/UVM testbench. I use the generated SystemVerilog wrapper module of the matlab function, and I can see that only certain SystemVerilog types are supported for the input/output ports of the wrapper module, according to the page below,
In my case, in the matlab-world an input of type 'fi(0,1,14,0)' (signed 14-bit) is converted into a 'shortint' and an input of type 'fi(0,1,18,17)' (signed 18-bit) is converted into an 'int'. This means an additional step of manual 'type-conversion' has to be done by the user in order to drive the wrapper module for each and every input and output, and this tends to be very error prone, in cases where there are several input/outputs. In an ideal world, I would have expected the types logic [13:0] and logic [17:0] respectively for my example.
My question is, why is dpigen restricted to a limited set of types instead of using bit-vectors in the SystemVerilog world ?
From such a sophisticated code-generation tool, it should be possible for the user to have an automatic seamless interface to the Systemverilog testbench, without intoducing manual steps.
regards
