trigger block in simulink

2012 9 4
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I need to have a trigger block, which should trigger only one block at a time.
For example
I have 2 blocks A , B connected to the trigger block T, this triggering block T should trigger one of these A, B blocks at different instances. i.e trigger A at instant 0, A at instant 1, B at instant 2, A at instant 2 and so on.
which triggering block should i use?
And should i use any code to have this timed triggering
waiting fr ur valuable response
Thank you

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TAB
TAB 2012-9-5
Can you clarify the exact trigger pattern you want?
A,A,B,A,B,A,B,A,B....... contiuously
OR
A,A,B,A,B ie only five triggers ?
Rahul kumar
Rahul kumar 2012-9-5
it should fire contiously.. as i am trying to convert a synchronous data flow graph into a synchronous block diagram..!
when A block is triggered should produce some tokens ( 2 for my model) when B block is triggered should consume some tokens ( 3 for my model)
Rahul kumar
Rahul kumar 2012-9-5
编辑：Rahul kumar 2012-9-5
So like this i need to form a producer-consumer model!! the trigger can be in any order.!
But preferably A,A,B,A,B because when A is fired twice (2+2 tokens produced), it is sufficient for B to get 3 tokens from double firing of A, then so on.

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TAB
TAB 2012-9-5
编辑：TAB 2012-9-5

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[Edited]
Please see the model snapshot below:

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Rahul kumar
Rahul kumar 2012-9-5
Can u please explain what is happening in the switch block and what is the purpose of repeating sequence stair?
TAB
TAB 2012-9-5
@Rahul kumar: Please let me know that the is as expected or not. I will explain the working.
Rahul kumar
Rahul kumar 2012-9-5
Yes the trigger sequence is as expected!! thank you,
And which block did you use for A, B is it triggered subsystem block?
TAB
TAB 2012-9-5
编辑：TAB 2012-9-5
Yes it is triggered subsystem with rising edge trigger type.
Initially at t=0, output of unit delay block will be 1 (Initial condition:1). So switch block will send the input-1 to the output which is equal to 1.
Afterward, output of switch block will come from input-3 connected to repeating sequence stair.
Repeating sequence stair will generate the sequence of 0 & 1 continuously.
So
Sample Time : 0 1 2 3 4 5 6 ....
Switch Blk Intput-1: 1 1 1 1 1 1 1 ....
Switch Blk Intput-2: 0 1 0 1 0 1 0 ....
Switch Blk output : 1 1 0 1 0 1 0 ....
NOT Blk output : 0 0 1 0 1 0 1 ....
Hope now it is clear.

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Azzi Abdelmalek
Azzi Abdelmalek 2012-9-4
编辑：Azzi Abdelmalek 2012-9-4

1 个投票

try this
  1. set all sample time block to ts
  2. set initial value of unit delay block to 1

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Rahul kumar
Rahul kumar 2012-9-4
can you please explain what is happening in the given diagram above..! the signal is starting from where?
thank you
Azzi Abdelmalek
Azzi Abdelmalek 2012-9-4
  1. the initial value of "unit delay" block is set to 0 by default. you can change it.
  2. then the first value of signal 1 is 0 while the first value of signal 2 is 1 not(0)
  3. at the next step signal1=1 while signal2=0 and so
Azzi Abdelmalek
Azzi Abdelmalek 2012-9-4
can you explain how are you triggering your blocks
Rahul kumar
Rahul kumar 2012-9-4
ya this triggering looks correct if we trigger one after one ie. A then B then A so on.. but i need t´rigger like this A,A,B,A,B.
Azzi Abdelmalek
Azzi Abdelmalek 2012-9-4
are you working with specified sample time?
Rahul kumar
Rahul kumar 2012-9-4
yes having a sample time would make more sense, as the block produces outputs and if appropriate, updates its internal state at the given sample time. but i dont know wat sample time to use.
Azzi Abdelmalek
Azzi Abdelmalek 2012-9-4
depends on what system are you working on? check the updated model
Azzi Abdelmalek
Azzi Abdelmalek 2012-9-4
I think you can do it with inherited sampe time
Rahul kumar
Rahul kumar 2012-9-4
编辑：Rahul kumar 2012-9-4
Can u pls explain the block again if u dont mind, wat is the clock and constant block doing and what is that >0 port also doing in the block.
Thanks in advance.
Azzi Abdelmalek
Azzi Abdelmalek 2012-9-4
编辑：Azzi Abdelmalek 2012-9-4
  1. the clock block is calculating time
  2. the switch block output is from constant 1(third input) when time(second input)>0 ;else its from the (unit delay-not) block (first iput)
that means at step 1 the signal1=1 and signal2=0; at step 2: sgnal1=1 ; signal2=0; at step3: signal1=0;signl2=1
do not forget to set initial value of unit delay block to 1 and the threshold of switch block to 0 and threshold condition of switch block to >threshold
Rahul kumar
Rahul kumar 2012-9-4
actually u said, If the time(second input)>0 output from constant block 1 else from(unit delay-not) block
so is the time(second input) keeps changing at different instances?
and at step 2 the o/p from not block also 1 and from the constant block also 1, so how it works at this step.
at step 3 othe o/p from not block is 0 and from the constant block also 1, so how it became signal 1=0 and signl2=1
so for bothering you.
Thanks for clarifying
Azzi Abdelmalek
Azzi Abdelmalek 2012-9-4
you don't bother me. but I ask you to connect signals to a scope, and simulate and look what is going on
Rahul kumar
Rahul kumar 2012-9-4
ya i ll simulate with the display n let you know!!
thank you
Rahul kumar
Rahul kumar 2012-9-5
I simulate it with display,on the first o/p, signal 1 is 0 and signal 2 is 1 and the simulate is nt happening continuously. it stops after one simulation.
And what is the decimation value to use in the clock? it has some effect?
Rahul kumar
Rahul kumar 2012-9-5
编辑：Rahul kumar 2012-9-5
the simulation is running continuously if i set the simulation time to inf, but i cannot view the o/ps from the signals, as it is changing very very fastly in the display block.
Is something to change so that the o/p changes after a finite time, so that it will be easy to view
TAB
TAB 2012-9-5
编辑：TAB 2012-9-5
What about scope block ?
Rahul kumar
Rahul kumar 2012-9-5
ya i connected with Scope block and saw, it gave a continuous triangular waveforms in scope 1 and it gave a continuous square waveform in scope 2.
Azzi Abdelmalek
Azzi Abdelmalek 2012-9-5
  1. Exactly. I can't explain the differents shapes, from the modlel: signal2=not(signal1), maby someone else can explain this.
  2. Now use "to workspace" block, you will observe that signal1= 1 1 0 1 0 1 and |signal2= 0 0 1 0 1 0 1 0 thats what we were looking for.
  3. Then try to use these signals and tell us what is the rsult
Rahul kumar
Rahul kumar 2012-9-5
Can u pls tell me where to view the output from 'To workspace' block
Azzi Abdelmalek
Azzi Abdelmalek 2012-9-5
you can view it on workspace, just set the parameters of "to workspace" blocks
  1. Variable Name = y1 for example for the first signal
  2. Save format to array
Rahul kumar
Rahul kumar 2012-9-5
编辑：Rahul kumar 2012-9-5
Ya i can view the output well in the work space as expected..!! thank you, can you please help me to view the the same output in a display block inside the simulink.. The outputs 1 and 0 should change afer a finite time (say 1sec)
As of nw it is changing very very fastly in the display block, i cannot view whether it is 1 0r 0 in the display block
Azzi Abdelmalek
Azzi Abdelmalek 2012-9-5
because you are not runing on real time
Azzi Abdelmalek
Azzi Abdelmalek 2012-9-5
编辑：Azzi Abdelmalek 2012-9-5
if you have a "real time windows target" toolbox, you can simulate on real time
Rahul kumar
Rahul kumar 2012-9-5
oh ok, So is it possible to do it on real time?
Azzi Abdelmalek
Azzi Abdelmalek 2012-9-5
编辑：Azzi Abdelmalek 2012-9-5
yes, if you are on 64 bit you can do it just on normal, the extarnal mode is allowed only on 32 bit (its more efficient)
Azzi Abdelmalek
Azzi Abdelmalek 2012-9-5
when I added 2 not blocks I 'm not getting triangular signal(above model)
Rahul kumar
Rahul kumar 2012-9-6
@azzi abdelmalek. hw to accept your answer?
Azzi Abdelmalek
Azzi Abdelmalek 2012-9-6
you can't accept two answers
TAB
TAB 2012-9-6
编辑：TAB 2012-9-6
I think the first output (trigger block 1) was showing ramp because it's type was double. Now after connecting to logical block (2 NOT blocks) output is as expected as is it converted to boolean.
Alternative of adding 2 NOT block is change the datatype of Constant block to boolean.
Azzi Abdelmalek
Azzi Abdelmalek 2012-9-6
Exactly, that what I was going to post. I set data type of a constant block to boolean and now it works. Thanks TAB
Rahul kumar
Rahul kumar 2012-9-9
hi i have another task also to do it
I am trying to convert a synchronous data flow graph into a synchronous block diagram in simulink..!
I have 2 blocks A and B with a FIFO in between them for buffer.
A has to produce 2 tokens in a iteration and 2 on the next. These 2 tokens from 1st iteration has to be stored in a block(FIF0 queue) and if it is reaches 3 ( on next iteration) it should trigger B
I need to figure a FIFO model with some specifications.
-FIFO register size 4, as we should store 4 tokens
-The criteria for firing of A (producing 2 tokens) is that there should be 2 free space at the head of FIFO
-The criteria for firing of B (consuming 3 tokens) is that there should be 3 tokens available at the tail of FIFO
Any ideas pls lets discuss!!
Thank you
Azzi Abdelmalek
Azzi Abdelmalek 2012-9-9
why do'nt you post it in another question?
Rahul kumar
Rahul kumar 2012-9-9
ya i posted bt no one commented.. so ly trying to get help from u
Rahul kumar
Rahul kumar 2012-9-10
Any ideas azzi abdelmalek?

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