HDL IP block with more than one type of AXI interface

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Michael Du
Michael Du 2020-1-21
回答： Charan Jadigam 2020-3-24
The idea is to generate the HDL IP blocks using the external PL DDR3 memories with both AXI4 Master and AXIS interfaces. The data are sent in in AXIS mode, lots of memory intensive calculation is done using the AXI4 Master read/write IF and then the data are read out in the AXIS mode, as shown in Fig. 1.
In the workadvisor flow, the protocol mapping for the external memory DDR3 interface is limited to AXI4 Master read and write, and there is no other mapping left for the protocol mapping for streaming data in. Shown in Fig. 2.
What is the best way to have multiple AXI interfaces for the IP block generation?
Fig. 1
AXIS-AXI4 module.png
Fig. 2
AXI4-IF_AXIS-IF.png

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回答（1 个）

Charan Jadigam
Charan Jadigam 2020-3-24
Hi,
The feature of adding multiple AXI interfaces in a single IP is introduced in MATLAB version R2020a.This can be found in the release-notes.
The steps to be followed to add AXI interfaces can be found here.

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