HDL Coder Filter Latency

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Hi

Ive complied a fully paralell FIR filter using the FilterDesigner and HDL Coder and it reported the latency as 2. I am struggling to understand what the latency is exactly, is it the number of clocks required for a valid output? - 1 clock for multiplication and another for summing, but if so would the delay pipeline not also require a clock cycle?

-- -------------------------------
-- Filter Structure  : Direct-Form FIR
-- Filter Length     : 65
-- Stable            : Yes
-- Linear Phase      : Yes (Type 1)
-- Arithmetic        : fixed
-- Numerator         : s16,15 -> [-1 1)
-- Input             : s16,15 -> [-1 1)
-- Filter Internals  : Full Precision
--   Output          : s33,30 -> [-4 4)  (auto determined)
--   Product         : s31,30 -> [-1 1)  (auto determined)
--   Accumulator     : s33,30 -> [-4 4)  (auto determined)
--   Round Mode      : No rounding
--   Overflow Mode   : No overflow
-- -------------------------------------------------------------