Error in Test Harness Generation in SIL Verification Mode

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creative 2020-5-11

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此问题的直接链接

https://ww2.mathworks.cn/matlabcentral/answers/524567-error-in-test-harness-generation-in-sil-verification-mode

评论： Jesús Zambrano 2020-5-12

Hello,

I am trying to generate SIL testing (Right Click on subsystem->Create Test Harness -> Select SIL) for a subsystem, but i get following Warnings and matlab crashes..could any help me out to resolve the issue ?

Port number 2 specified in 'port_label' drawing command exceeds the number of input ports of 'untitled/SIL Block' [22 similar]

Component:Simulink | Category:Block warning

Port number 2 specified in 'port_label' drawing command exceeds the number of output ports of 'untitled/SIL Block' [2 similar]

Thank you.

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Answer 1

Jesús Zambrano 2020-5-11

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https://ww2.mathworks.cn/matlabcentral/answers/524567-error-in-test-harness-generation-in-sil-verification-mode#answer_431827

I assume that the subsystem is part of a Simulink model, correct? Before creating the harness for the subsystem, make sure that the inport/outport ports of this subsystem are specified (data type, dimensions, sample time).

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creative 2020-5-12

Thank you. It Worked. Yes subsystem is part of simulink model.

Also i see that when i generate SIL testing , along with the subsystem for which SIL is performed all other subsystems are build too. This I did not understand why is it so?

Jesús Zambrano 2020-5-12

You can create a harness for a top level model (showing a badge on th elower left of the canvas) or for a model component (showing a badge on the lower right of the component).

Please see more information in the following link:

https://se.mathworks.com/help/sltest/ug/select-test-harness-properties-for-your-task.html

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