Cannot Validate Phase Locked Loop on F28069M Launchpad

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Rolando Aguilera 2020-6-14

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https://ww2.mathworks.cn/matlabcentral/answers/547854-cannot-validate-phase-locked-loop-on-f28069m-launchpad

评论： Spoorti Pattanashetti 2024-5-23

Hello everyone,

Currently Im testing my power electronics generated code. In order to assess it, Im breaking the model and testing part by part. Now Im testing the PLL, so in order to test it, I generate the code for the PLL embedded on a 30KHz ADC interrupt. Inside the interrupt, I process the PLL and send the data through UART and catch the data on another simulink model and display it on a scope.

The PLL model has been simulated on simulink with expected results, however once I generate the code and deploy into the MCU, it doesnt match the simulation. Im attaching the model for reference.

Any help will be appreciated.

Thanks,

Rolando

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Rolando Aguilera 2020-6-17

PLLInsideADCInt.slx

Hello Joel,

Upon endlessly tests I made the PLL worked. What I saw is that code generation has trouble when using "preexisting" blocks as I simulated a synchronous reference frame PLL with a simulink defined integrator vs a custom made one.

Waveform generation can be seen from the UART simulink model attached beforehand or by using CCS debugger graphing window.

Im attaching the model, for someone who might benefit in the future.

Thanks,

Rolando