Send Serial Communication data to FPGA

Question

Hugo Pontes 2020-6-16

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https://ww2.mathworks.cn/matlabcentral/answers/549342-send-serial-communication-data-to-fpga

回答： Phan Phat 2020-9-2

Hello. I am trying to test the communication between MATLAB on my computer and an FPGA I programmed. What I'm attempting to do is to send a number and have the FPGA return that number times 2. I am using an 8bit fixed point representation with 4 integer bits and 4 fractional bits.

My code is the following:

int=4;
frac=4;
data = 3.25
fixdata = dec2fix(data,int,frac);
senddata = bin2dec(fixdata);
s = serial('COM5','BaudRate',9600,'TimeOut',0.1,'Terminator','LF');
fopen(s);
fwrite(s,senddata,'uint8');
a=fix2dec(dec2bin(fread(s),int+frac),int,frac)
fclose(s)
delete(s)

fix2dec and dec2fix are custom made functions that transform decimal numbers into their closest fixed number representation and vice versa.

So supposedly the data (3.25) will be input, then its fixed point equivalent will be calculated, which will be 0011.0100 then it is converted back to a decimal considering a uint8 format (00110100 = 52). Am I right to assume that if I send that decimal (senddata = 52) the laptop tx pin will output 00110100? Do I need to send a start bit before?

As it stands, I always get 11111111 as an output, except for when data is 3.5 which for some reason which yields 11111110.

According to FPGA simulations, if the matlab tx output was 0 (start bit) + 00110100(data bits) +1(stop bits), the output should be the correct fixed point represenation of 6.5 = 01101000

What is wrong here? If nothing is I suppose the problem is in the FPGA

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Andrey Smolyakov 2020-6-16

If I understand documentation correctly (here, section 'StopBits'), you are right, and MATLAB will send start bit, 8 bits of your data, and stop bit. So I guess that nothing is wrong here, and the problem is on the FPGA side.

Hugo Pontes 2020-6-17

I've been getting readings from an oscilloscope and I've checked that this is true, MATLAB outputs a three in binary but the timing of the FPGA is wrong and doesn't decipher it correctly

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