I understand that you are trying to build a resettable clock system which can reset itself and start counting whenever an external signal is triggered.
I’ve run the model developed by you and have been able to reproduce the same graph of the output signal as described. The reason, as stated by you correctly, is that the external signal is unable to reset the timer control and therefore, the timer control (Timer stop in the figure) runs for only the remaining time i.e. 4s – the time elapsed before the trigger got high, justifying the obtained output.
A simple solution to this would be to remove the timer stop block altogether (it is doing nothing apart from the desired action of keeping track of the 4s) and to add the timer control to a ‘Compare to Constant’ block as shown.
Here, as per the desired requirements, 4 has been set as the constant.
At each time step, check for the difference between the current simulation clock time and the time which was stored in the memory the last time the clock reset itself. Whenever the external signal gets high, the system should reset, therefore the ‘Ext.signal’ is connected with a NOT gate. The AND gate would ensure that the switch condition only gets true when both the ‘Ext.signal’ is false and the time difference is less than the desired period.
Simulating the same, we can get the desired output. The blue lines indicate the triggers.
’Ext.signal’ has been taken as a pulse generator with 0.01% duty cycle repeating after 10s.
Hope this helps!
