When using Simulink Desktop real-time external mode, there is a serious delay and mismatch between the data sent by UDP to the FPGA hardware and the data received by UDP.

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I sent a sine signal to the FPGA hardware through the packet output module, and at the same time the FPGA hardware sent the signal back and received it with the packet input module. There was a large delay and mismatch between the two.How can I fix it?

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Altaïr
Altaïr 2025-4-14
The issue might stem from the internal buffer of the UDP driver, which stores unread packets until it reaches capacity. It's important to note that the Packet Output block sends a packet at each time step, regardless of changes in the block input value. Meanwhile, the Packet Input block reads just one packet per time step, even if multiple packets are queued in the incoming buffer. What may seem like a delay due to low performance could actually be a result of a long queue of unprocessed packets being handled one-by-one, arriving faster than they are processed.
To address the long queue in the buffer, consider setting the sample time of the Packet Input block to a value shorter than the expected period of new packet arrivals. Additionally, use the Data Ready port to determine when a new packet has actually arrived.
If reducing the sample time isn't feasible and there's a need to read only the newest message, the previous messages can be discarded by utilizing the Data Ready port of the Packet Input block. This can be achieved by placing the Packet Input block inside a While Iterator subsystem and driving the While condition with the Data Ready port. This setup will ensure messages are read one-by-one as long as they exist, with only the data from the last message displayed at the output of the While Iterator block. Inside the While Iterator subsystem, all blocks should have their sample rate set to -1, as execution is based on the While condition.
For further insights, here’s a helpful MATLAB Answer on this topic:

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