Why can I not specify a bus to have infinite sample time (constant)?

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max.s 2020-7-29

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评论： max.s 2020-10-26

sample.slx

Please have a look at the attached example.

I have a bus in which one element is always constant. I'd like to enforce / reinforce that property by setting the sample time on the bus element out block of the signal to inf, which produces the error:

In '<hidden_signal_specification_block> inserted for "In.const" (sample/Subsystem1/Bus Element In)', the parameter 'SampleTime' must be real and finite. Constant (inf) sample time is not allowed.

What's the explanation for this error and what should I do to fix it?

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Answer 1

Urmila Rajpurohith 2020-10-23

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Hi

From the error message i am assuming that the block is expecting the sample time which is real and finite.

For a block to allow constant sample time, it should hold the following conditions

The block has no continuous or discrete states.
The block does not drive an output port of a conditionally executed subsystem

For more information on Types of Sample time refer to the below documentation:

https://www.mathworks.com/help/simulink/ug/types-of-sample-time.html

Hope this helps!

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max.s 2020-10-26

But AFAIK the gain block doesn't have continuous or discrete states, it should be able to perform normally on a constant input. Your information makes sense but I'm having trouble to understand how this applies to this simple model.

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