清空筛选条件
清空筛选条件

Can't generate .bit nor .sof file with FIL Wizard on Ubuntu.

3 次查看（过去 30 天）
Eduardo Flores
Eduardo Flores 2020-12-27
回答： YP 2022-11-21
After compiling an FPGA in the loop simulink model with VHDL Verifier for Xilinx or Altera devices the new model with the FIL object appears. On windows, a new terminal shows that a new bitstream is being generated but on Ubuntu 18.05, no file is ever created. Am i missing a configuration step?
  1 个评论
Cau Tran
Cau Tran 2022-8-11
I also had this problem. Can anyone give me advice for this one?
FIL does not generate the bitstream file.

请先登录，再进行评论。

请先登录，再回答此问题。

回答（1 个）

YP
YP 2022-11-21
Can you check if xterm is installed?
FYI https://www.mathworks.com/help/hdlverifier/ug/troubleshooting-fil.html

类别

在 Help Center 和 File Exchange 中查找有关 FPGA, ASIC, and SoC Development 的更多信息

标签

Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!

Translated by