Can't generate .bit nor .sof file with FIL Wizard on Ubuntu.

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Eduardo Flores 2020-12-27

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https://ww2.mathworks.cn/matlabcentral/answers/703492-can-t-generate-bit-nor-sof-file-with-fil-wizard-on-ubuntu

回答： YP 2022-11-21

After compiling an FPGA in the loop simulink model with VHDL Verifier for Xilinx or Altera devices the new model with the FIL object appears. On windows, a new terminal shows that a new bitstream is being generated but on Ubuntu 18.05, no file is ever created. Am i missing a configuration step?

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Cau Tran 2022-8-11

I also had this problem. Can anyone give me advice for this one?

FIL does not generate the bitstream file.

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YP 2022-11-21

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Can you check if xterm is installed?

FYI https://www.mathworks.com/help/hdlverifier/ug/troubleshooting-fil.html

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Code Generation HDL Verifier Algorithm Verification FPGA-in-the-Loop

FPGA, ASIC, and SoC Development HDL Verifier Algorithm Verification FPGA-in-the-Loop

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