How to set the clock frequency when converting a simulink model to HDL code.
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Hello,
I have designed a sine pwm model in the simulink using sine-sawtooth waveform comparison method. The model working perfectly in the simulink. I have converted the same to verilog code using HDL coder(ver 2.1). The target is Altera Cyclone II with device EP2C35F672C6. The board clock frequency selected is 50 Mhz., but generated output is much higher than the desired frequency (50 Hz).
Is it possible to set the global clock frequency in the model?
or is there any method to set the clock frequency while converting to the desired target (say Altera Cyclone or Spartan II Xilinx).
Thanks and regards
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Tim McBrayer
2013-4-17
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If your board frequency is fixed, and you want a specific output frequency on your sine wave, you will need to understand the relationship between your clock frequency and output frequency. How many Simulink clock ticks does it take to generate one full output sine wave cycle?
If you set your Simulink solver to fixed-step discrete, and also set your fundamental sample time to 1/50MHz = 2E-08 sec, you should then be able to update your design to get a 50Hz output sine wave in Simulink. Note that your desired output is a million times slower than the clock rate of the board. You can update the actual sine wave discretization in your design, use rate transition blocks to reduce the output frequency and/or signal generation, or use the HDL Coder oversampling factor to essentially slow down the system clock.
1 个评论
shauk
2017-5-2
Hallo
what would i need to do, when i have interpolation filters in my design, lets say my input is 44.1 kHz and my output is 11.2 MHz, with two upsampling filters in between. My system frequency is 37 MHz, how do i set the simulink fundamental sample time?
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