Ambiguous sorted order detected due to use of triggered subsystem(s) and/or Model blocks in a loop.

Question

poonam 2021-1-22

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https://ww2.mathworks.cn/matlabcentral/answers/724053-ambiguous-sorted-order-detected-due-to-use-of-triggered-subsystem-s-and-or-model-blocks-in-a-loop

回答： Juan Sagarduy 2021-2-25

I am working on a simulation of an mixed circuit. The circuit involved some input op-amp circuit, comparator(let's say pre-analog) and logic circuit and transistor circuit(post-analog). The analog circuit is made of simscape modules and logic circuit made of simulink modules.

The pre-analog_circuit provids the pulsating signal which is used as clock signal to the logic circuit. Logic circuit output swithching transistors. ((Image attached))

When the programm is compiled it is giving this below error.

Ambiguous sorted order detected due to use of triggered subsystem(s) and/or Model blocks in a loop. See Subsystem Examples in the Simulink library for valid and invalid examples of triggered subsystems
Component:Simulink | Category:Model error

As I can understand I need to add the trigger to my logic circuit. However I am still getting an similar error with solver configuration.

I have explored the similar errors past questions but not helped much.

Can someone please help me understand where I am doing wrong? Logic circuit and digital circuit attached.

Ambiguous sorted order detected due to use of triggered subsystem(s) and/or Model blocks in a loop. See Subsystem Examples in the Simulink library for valid and invalid examples of triggered subsystems
Component:Simulink | Category:Model error
The trigger input port of triggered subsystem or Model block 'Test_Model_Analog_Digital/ Logic Testing using Simulink/Logic Testing using Simulink' is involved in a loop. This causes the  trigger signal at time t to be dependent on the output of the triggered subsystem or Model block at time t, resulting in an ambiguous execution order. You can use a Memory to break the loop.
Component:Simulink | Category:Model error
Input ports (1, 2, 6, 7) of 'Test_Model_Analog_Digital/ Logic Testing using Simulink/Solver Configuration' are involved in a loop containing triggered subsystem(s) and/or triggered Model blocks.
Component:Simulink | Category:Model error
Input ports (1) of 'Test_Model_Analog_Digital/TL594 Logic Testing using SimScape/TL594Logic Testing/Manual Switch3' are involved in a loop containing triggered subsystem(s) and/or triggered Model blocks.
Component:Simulink | Category:Model error
Input ports (1) of 'Test_Model_Analog_Digital/ Logic Testing using Simulink/Solver Configuration' are involved in a loop containing triggered subsystem(s) and/or triggered Model blocks.
Component:Simulink | Category:Model error
Input ports (1) of 'Test_Model_Analog_Digital/ Logic Testing using Simulink/Solver Configuration' are involved in a loop containing triggered subsystem(s) and/or triggered Model blocks.
Component:Simulink | Category:Model error
Input ports (1) of 'Test_Model_Analog_Digital/ Logic Testing using Simulink/Solver Configuration' are involved in a loop containing triggered subsystem(s) and/or triggered Model blocks.
Component:Simulink | Category:Model error
Input ports (1, 2, 6) of 'Test_Model_Analog_Digital/ Logic Testing using Simulink/Solver Configuration' are involved in a loop containing triggered subsystem(s) and/or triggered Model blocks.