Xilinx System Generator for DSP is not used as part of the standard workflow for the example, HW/SW Co-Design with AXI4-Stream Using Analog Devices AD9361/AD9364. Do you mean Xilinx Vivado Design Suite? If so, Vivado 2018.2 is supported in MATLAB R2019a for this example.
For IP Core Generation workflows, the reference designs provided are implemented and tested against a specific version of Xilinx Vivado, and so there is a requirement to use that version of Vivado in your own workflows.
Furthermore, the Communications Toolbox Support Package for Xilinx Zynq-Based Radio and the reference designs that ship with it has its own requirement for a specific Vivado version that it has been implemented and tested against.
In Step 1.2 Set Target Reference Design of the HDL Workflow Advisor, you can select the checkbox titled Ignore Tool Version Mismatch. This will convert any errors about incorrect Vivado tool versions to warnings instead, and may allow you to proceed, but this is not a guarantee, as the reference design has not been implemented and tested against this version as noted above.
It is recommend to use the Vivado version supported by the MATLAB release you are using:
- For MATLAB R2020a, this is Vivado 2019.1
- For MATLAB R2019a, this is Vivado 2018.2
Regards,
Martin
