Error in importhdl how to solve?

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I am trying to import a verilog module that calls other submodules. Whenever, I try to import from HDL to simulink, I am getting these errors. I don't even any clock in my design.
Module instance creation failed for 'x' module and 'y' module instance, due to clock inference limitation. Rerun with clock bundle name-value pair. More information.
Hdl Import parse failed.
Error using privimporthdl
Importhdl failed.
Error in importhdl (line 78)
privimporthdl(hdlInSrc, varargin{:}) - Show complete stack trace
  2 个评论
Khalala Mamouri
Khalala Mamouri 2021-2-23
Hello,
I currently facing the same issue; have you solved the problem ?
Best regards
lakhdar
Nadatimuj
Nadatimuj 2021-2-23
编辑:Nadatimuj 2021-2-23
I found that I have used some posedge in my code. And also some variables that sound like clock and reset. Matlab thought those are real clocks. If it finds same clocks between the modules, it gives this error. I couldn't solve it though.

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采纳的回答

Stefanie Schwarz
Stefanie Schwarz 2022-1-5
编辑:Stefanie Schwarz 2022-1-5
Here is a list of supported constructs with importdhl:
If you encounter the same error, please contact MathWorks Technical Support with your Verilog source code so we can investigate.

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