Error beetween two methods: Simulink and Verilog(after convert by HDL coder)
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Dear My friends!
Now i have some problems in HDL simulink coder that need your helping. When i convert my code from simulink to verilog and after that i cosimulate it with modelsim, I have got an error between two results.
http://i1297.photobucket.com/albums/ag25/Dung_Pham_Van/error_zps3efd15af.gif
Anyone have any experimental to solve this problem?? please give me some suggestions.
Thanks with best regard!
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Tim McBrayer
2013-5-7
0 个投票
It looks like the two waveforms are identical, but time-shifted. Often Simulink HDL Coder will need to insert latency into the HDL design based on the configuration and optimizations chosen. The amount of introduced latency is reported on the MATLAB console and also in the HTML report, if generated. Could this be the source of the shift? Are the results identical save for the time shift?
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