Resolving missing coverage using simulink design verifier and not by using simulink test

2021 6 19
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更新时间：2021 6 28
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I have a complex stateflow subsystem which has given me less coverage while using simulink coverage and simulink design verifer license. Is there any formal method to resolve the missing coverage without using simulink Test license nor do I use reactis license
My approaches so far
I have even tried generating multiple .cvt files (coverage files) but thats not helping me to maximise the coverage.
Does entering range of min and max values of inputs help to maximise the coverage.

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Simulink Test will help you manage and construct a test-suite - I am not sure it will help you in achieving coverage on its own. For example, Simulink Test can help if you want to manually author test-case in additio to auto-generating test-cases from Simulink Design Verifier, or if you want to manage test-suites across multiple components (models/subsystems etc.), and automate test-execution, coverage measurement etc.
Have you tried identifying dead-logic in the state-chart? Are there "unsatisfiable" objectives in the chart? Have you analyzed the chart for design-errors?
Entering min-max values for inputs would make the formal analysis problem more tractable, it can convert some "undecided" objectives into "satisfied". But you do need to be careful that the ranges reflect the actual intended usage of the stateflow chart. If you over-constrain the ranges, some objectives in the chart may become unsatisfiable.
Could you also clarify the workflow you are using with cvt files? The cvt files save coverage data in a file, and by themselves would not help maximizing coverage.

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Rahul
Rahul 2021-6-20
Thanks for the answer. The workflow I used for cvt files is as follows. I used to first enable coverage analysis in model configuration setting and get the intial coverage by simulating the model. Then I used to save that file of Cvt and for the second run I will use the intial coverage cvt file that I obtained in run 1 and used to tick the checkmark that ignore the coverage objectives of the satisfied case. I thought by doing so, it will improve the missing coverage by auto generating test cases for unsatisfied objectives. But I couldnot see much difference in coverage by comparing run1 and run2
So the sequence of steps you follow is:
  • Simulate the chart with default inputs and capture the coverage achieved in a cvt file (initial.cvt)
  • Use initial.cvt as input to Design Verifier to generate test-cases while ignoring the coverage objectives satisfied by initial.cvt
It appears that there are transitions/decisions in your Stateflow chart that Design Verifier is having difficulty solving. This will need some analysis of the chart to see if you can identify a transition/decision that is a bottle-neck for the analysis. Maybe it is guarded by a long-running timer - which leads to states that are currently not covered. I would suggest using the test-case extension workflow to generate additional test-cases. Some resources:
Note that more recent versions of Simulink Design Verifier have automated some of the steps mentioned in the resources above, when a harness model is provided as input to analysis.
Rahul
Rahul 2021-6-21
Thank you very much for the help and response. I will look into the resources you listed out
Hai, is there a way to conevert the CVT data to EXcel? inca se i want to view and analyse the coverage data inexcel?
Rahul
Rahul 2021-6-28
Hi,
Probably you can post as a new question from your account and you may get it as an answer from other people or mathworks staff

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