Based on my understanding, you want to generate HDL code for PWM. In order to run the model on fpga, the model parameters have to be configured to be compatible for HDL code generation. Please refer to the following list of model paramaters, which have to be set accordingly for code generation. The second criterion from the above link is to set the solver step size to auto, which implies that solver decides the step size, removing the option of manual assignment. Additionally, hdlsetup can also be run to set the model parameters for HDL code generation.
The target frequency of FPGA can be changed manually from HDL workflow advisor. Additionally, hdlset_param function can be used to set the target frequency from command line