Change RF parameters from matlab using libiio on adrv9361z7035

39 次查看（过去 30 天）
aeon jose
aeon jose 2021-7-8
编辑： aeon jose 2021-8-3
I am using adrv9361z7035 board. I wanted to control the RF parameters OF AD9361 from matlab using libiio. As the first step I have installed and setup Communications Toolbox Support Package for Xilinx Zynq-Based Radio. With the Linux image copied to the SD card, i was able to run the example.
1) I wanted to change the RF parameters like sampling frequency, LO frequency, gain, gain mode, etc from matlab with the help of libiio. Is there any APIs for that.
2) Will i be able to do the same if i load a cutom binary file?
By using the system command i am able to change few RF parametrs from matlab wilth iio commands(image:system(iio_cmd)).
I tried to follow this link to capture samples and save it
https://wiki.analog.com/resources/tools-software/linux-software/libiio/iio_readdev
3) I was able to do so with the image provided while setting up communication toolbox. But when i try to capture using a custom binary,even with qpsk example model, I am getting buffer error "Unable to refill buffer: Unknown error".
Any inputs will be helpfull. Thankyou.

请先登录，再回答此问题。

采纳的回答

Martin Enderwitz
Martin Enderwitz 2021-7-9
The Communications Toolbox Support Package for Xilinx Zynq-Based Radio is based on the reference design provided by Analog Devices, with some modifications. Support for RF parameter configuration and data streaming is provided through MATLAB APIs that use libiio. As such, it is recommended you use the MATLAB APIs for all interaction with hardware using this SD card image to ensure successful operation, as it is these APIs we design and test against.
1) Please see the following documentation for information on how to use the provided system objects to configure RF paramters and transmit/receive data with the A9361:
Receive data from AD936x-based Zynq radio hardware - MATLAB (mathworks.com)
Send data to AD936x-based Zynq radio hardware - MATLAB (mathworks.com)
2) If the custom bitstream is generated using the supported Hardware-Software Co-Design workflow, then you will be able to use the same system objects with any custom bitstreams you generate, as this ensures it is compatible with the reference design on the FPGA:
Hardware-Software Co-Design Workflow - MATLAB & Simulink (mathworks.com)
3) Try using the documented capture method to receive data from the AD9361 a custom bitstream:
Capture contiguous RF data using Xilinx Zynq-based radio hardware - MATLAB capture (mathworks.com)
If you're still facing issues with any of the above, then please do let me know.
Regards,
Martin
  7 个评论
显示 5更早的评论
Martin Enderwitz
Martin Enderwitz 2021-7-16
Hi Aeon,
The documentation on Hardware-Software Co-Design I linked earlier gives a high-level overview of the architecture on the Zynq side that illustrates some of my answers below:
Hardware-Software Co-Design Overview - MATLAB & Simulink (mathworks.com)
  1. By default, DMA is used to transfer data from PS to PL. If you want to use AXI4 interconnect, you can follow the example here: HW/SW Co-Design with AXI4-Stream Using Analog Devices AD9361/AD9364 - MATLAB & Simulink (mathworks.com)
  2. BypassUserLogic effectively controls a multiplexer, that when set to true will route the data directly to/from the RF HDL IP to the DMA, bypassing the "User Logic" in the diagram.
  3. I'm not sure what you mean by bypass_rx, bypass_tx here - could you clarify?
  4. There are 2 different mechanisms here, depending on whether you use the "transmit" or "transmitRepeat" functions of the system object. transmit will stream data from MATLAB to the Zynq PS over the Ethernet connection, via libiio. This then goes through the Tx data path on the FPGA to the RF. transmitRepeat is slightly different, in that it will load a given waveform into DDR memory on the FPGA and then cyclically repeat that waveform until stopped. As such, there is no "live" streaming between MATLAB and the Zynq device at this point.
Hope that answers your questions!
Regards,
Martin
aeon jose
aeon jose 2021-8-3
编辑：aeon jose 2021-8-3
3. I'm not sure what you mean by bypass_rx, bypass_tx here - could you clarify?
While opening the vivado project created by the workflow we can see two blockes named bypass_rx and bypass_tx along with some other blocks.
I would like to know the operation of bypassing user logic from the hardware side.

请先登录，再进行评论。

更多回答（0 个）

类别

在 Help Center 和 File Exchange 中查找有关 Xilinx FPGA and SoC Devices 的更多信息

标签

产品


版本

R2021a

Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!

Translated by