How to assign the name of a (multiple) port while using HDL Coder generate RTL from simulink

Question

dayu lai 2021-7-29

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https://ww2.mathworks.cn/matlabcentral/answers/888157-how-to-assign-the-name-of-a-multiple-port-while-using-hdl-coder-generate-rtl-from-simulink

回答： Kiran Kintali 2021-8-6

Hi,

I am using HDL coder to generate RTL from simulink.

While in my simulink model, the port is not a single signal but a multiple signal, assume the port name is sig, and it contains 3 signals which shares the same signal path. After RTL generation, HDL coder automatically expand the sig into 3 signals, which are sig_0, sig_1, and sig_2.

My questions is how can I assign the expanded name? I donot like the sig_0, sig_1 and sig_2. In my design, I would like to assign it as sig_x, sig_y, and sig_z.

Thanks a lot!

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Answer 1

Kiran Kintali 2021-8-1

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https://ww2.mathworks.cn/matlabcentral/answers/888157-how-to-assign-the-name-of-a-multiple-port-while-using-hdl-coder-generate-rtl-from-simulink#answer_758257

Can you share a sample model?

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dayu lai 2021-8-5

see my comments.

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Answer 2

dayu lai 2021-8-5

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此回答的直接链接

https://ww2.mathworks.cn/matlabcentral/answers/888157-how-to-assign-the-name-of-a-multiple-port-while-using-hdl-coder-generate-rtl-from-simulink#answer_761172

See attachment.

demo_param is the parameter used in demo_sig.mdl.

demo_sig is a quite simple demo for describing the question.

demo_sig.zip contians the generated RTL named demo_sig.v(.v file can not be uploaded as attachment, so I zipped it)

As you see, input port of Demo is automatically expanded into in_0, in_1, in_2.

My question is can the input name in RTL changed into in_x, in_y, in_z (by setting somewhere)?

Another question is, how can I share the logic since the 3 path are totally the same? (In reallity, the data path logic could be much more complex than the demo, so logic sharing is quite import)

Thanks a lot!

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Answer 3

Kiran Kintali 2021-8-5

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https://ww2.mathworks.cn/matlabcentral/answers/888157-how-to-assign-the-name-of-a-multiple-port-while-using-hdl-coder-generate-rtl-from-simulink#answer_761817

编辑：Kiran Kintali 2021-8-5

>>As you see, input port of Demo is automatically expanded into in_0, in_1, in_2. My question is can the input name in RTL changed into in_x, in_y, in_z (by setting somewhere)?

We do not have _x, _y and _z naming scheme currently. Please reach out to MathWorks support for the naming request. Without going into the solution space the specification of the naming convention that you request can be tricky.

>> How can I share the logic since the 3 paths are totally the same? (In reality, the data path logic could be much more complex than the demo, so logic sharing is quite important)

To enable resource sharing of identical channels as shown in your design you need to use the StreamingFactor option on the subsystem. See the attached pdf file on the usage.

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dayu lai 2021-8-6

Thanks a lot!

I am successfully generate shared logic in this demo.

However, when the project comes larger. I tried again in the large project, streaming optimization is not successful:

SubsystemStreamingFactorSharingFactor

Activity30

Streaming Report

Subsystem: Activity

StreamingFactor: 3

Streaming optimization unsuccessful

Highlight streaming diagnostics

No legal streaming factor values available for this subsystem

Clear highlighting

Sharing Report

No subsystem(s) found with SharingFactor > 0

Do you have any idea about this?

BTW, I notice that there is another option named SharingFactor. What is that? Is there any introduction or application note on streaming factor and sharing factor?

thanks

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