Simulink model compare - always different

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Maik
Maik 2021-8-9
编辑： Ivan 2023-7-19
I have created a Matlab Simulink library. Everytime I save the library (without any modification) and compare it to the previous version (using the Matlab internal compare tool), a parameter called 'InterfaceData' has always changed. It seems that it has something to do with the bus definitions used in the library (?). It is very tedious to find the real differences between all these pesudo changes. So my question:
1.) What could be the reason for the change. How can I avoid it ?
2.) Can I define a filter rule to hide these changes (tried it already with 'New Filter' without success) ?

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回答（2 个）

Divyam
Divyam 2023-7-10
Hi @Maik,
You are correct in your assumption that this could possibly be a result of the bus definitions of your library. Any changes to the bus definitions, be it object properties or data types might lead to this change.
Here is what you can do to solve this issue:
  1. Maintain a GitHub repository and look at the changes after each commit (you can probably add the interface data folder to the git ignore file)
  2. Create a custom MATLAB script and filter out the data changes in the Interface Data files.
You can refer to the following documentation for help with your script: Compare two files or folders - MATLAB visdiff - MathWorks India
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Ivan
Ivan 2023-7-17
编辑：Ivan 2023-7-19
  1. InterfaceData folder is not a folder in the filesystem, it seems to be an internal structure in the SImulink file, so it can't be ignored with git.
  2. I can't find any instructions on how to integrate an arbitrary visdiff filter call into the comparison tool UI. The only options the comparison tool presents for filter are based on a fixed set of properties.

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Ivan
Ivan 2023-7-18
I reached out to MathWorks support and they provided the following information:
Unfortunately, this is a bug related to using Bus Element ports with Subsystem References. The corresponding development team is aware of this issue and is investigating this further to fix the issue in a future update or release.
For now, the best workaround is to use regular Inports and Outports to transfer the entire bus in conjunction with Bus Selector/BusAssignment/BusCreator blocks to split and use the bus within a Subsystem Reference.

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