HDL Verifier Self-Guided Tutorial

版本 1.0.0 (8.2 MB) 作者: MathWorks HDLVerifier Team
Learn how to verify an algorithm on FPGAs using MATLAB and Simulink.
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75.0 次下载
更新时间 2025/4/17
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HDL Verifier™ enables you to reuse your system-level design environment in your HDL design environment. You can test and verify RTL designs against golden reference models in MATLAB® and Simulink®, debug designs in third-party simulators or hardware, and generate testbenches and verification IP.
This tutorial is designed to help you learn about three of the most popular features of HDL Verifier: HDL Cosimulation, FPGA-in-the-Loop, and FPGA Data Capture. The tutorial shows you how you can use these features whether you develop HDL on your own or use HDL Coder™ to generate HDL from MATLAB or Simulink.
Contents
The Tutorial provides instructions to run HDL Cosimulation with MATLAB and Simulink, perform FPGA validation using FPGA-in-the-Loop simulation, and load signals from designs programmed into development boards into MATLAB using FPGA Data Capture. The tutorial has the following sections.
HDL Cosimulation with Simulink
  • Cosimulation with existing HDL code (i.e., hand-coded RTL workflow)
  • Cosimulation with HDL code generated by HDL Coder
FPGA-in-the-loop (FIL) with Simulink
  • FPGA-in-the-Loop simulation with existing HDL code (i.e., hand-coded RTL workflow)
  • FPGA-in-the-Loop simulation with HDL code generated by HDL Coder
FPGA Data Capture
  • Data capture for existing HDL code (i.e., hand-coded RTL workflow)
  • IP core generation workflow that integrates FPGA Data Capture as part of IP core generation in an existing AXI Stream project
Examples are provided throughout the guide to illustrate concepts

引用格式

MathWorks HDLVerifier Team (2025). HDL Verifier Self-Guided Tutorial (https://github.com/mathworks/HDLVerifier-Self-Guided-Tutorial/releases/tag/1.0.0), GitHub. 检索时间: .

MATLAB 版本兼容性
创建方式 R2022b
兼容 R2022a 到 R2022b 的版本
平台兼容性
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版本 已发布 发行说明
1.0.0

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