DALSA Spyder 3 Camera Link decoder (for HDL Coder)

This block provides Camera Link pixel stream decoding for the DALSA Spyder 3 camera with 1k pixels and 2 taps (Model Nr. S3-20-01k40). It is intended for code generation with HDL Coder and was tested with Xilinx Vivado on an Artix 7 FPGA.

The block outputs the camera lines with a latency of one line period. This is because the pixels do not arrive ordered and have to be buffered. Valid line data is signalled by a high level on the line_valid output.