已回答 sample time mismatch
Thanks for the hint. Now it works, after changing sample time of the signal builder block to [0,1] (fixed in minor step).
13 years 前 | 1
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已回答 sample time mismatch
Is there any possibilty to debug the system, so that rate transition is not necessary (currently I cannot find the one with "con...
13 years 前 | 0
提问
sample time mismatch
after implementing a signal builder instead of single Steps, I get the following message:
"Incoming buses to block 'Thermosch...