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Sequential logic or combinational logic
Dear all, I have met a problem. It is that timing constraint is not satisfied when my design runs under a very high clock fre...

12 years 前 | 2 个回答 | 0

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Rate transition problem using upsample,repeat or rate transition block for generating HDL code
Dear all, I wanna change the rate of a signal from slow stepsize to fast stepsize. For instance, there is a sine signal. Its ...

12 years 前 | 0 个回答 | 0

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Problem of reciprocal building block in hdl code generation
Dear all, I used a periodic signal (Ts is period) as the input signal of the reciprocal of square root building block in simu...

12 years 前 | 1 个回答 | 0

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Why does the Fixed Point Advisor show a Trigonometric function as unsupported when using CORDIC approximation?
I also faced this problem when I used fixed point advisor & fixed point tool. Finally, I manually defined all bit widthes so as ...

12 years 前 | 0

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Problem in conversion from model to VHDL/Verilog HDL
Dear all Recently, I built up a model by basic blocks and stateflow in hdllib.Functional simulation results of floating point...

12 years 前 | 1 个回答 | 0

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