Feeds
提问
help for forcing simulink in order to run using ode4 (RG4)
Dear all, I have generate a motor model according to dq reference frame theory. The model is run without any problem, but I mus...
4 years 前 | 0 个回答 | 0
0
个回答提问
FPGA data capture setting problem
Dear all, I am trying to use FPGA data capture and following the instructions given in the page https://www.mathworks.com/help/...
5 years 前 | 1 个回答 | 0
1
个回答已回答
hdl coder work flow adviser block compability error
Dear Kiran Kintali, First of all, thanks for your fast answer. I have used all data either single or fixed-point and as you kno...
hdl coder work flow adviser block compability error
Dear Kiran Kintali, First of all, thanks for your fast answer. I have used all data either single or fixed-point and as you kno...
5 years 前 | 0
提问
hdl coder work flow adviser block compability error
Dear all, I have a model so as to control a pmsm. when I run the hdl workflow adviser to generate VHDL code, an error which is ...
5 years 前 | 4 个回答 | 0
4
个回答提问
hdl coder IO buffer error
Hi, I am creating a model using model based design for motor control. I have generated vhdl code and run implementation in viva...
5 years 前 | 1 个回答 | 0
1
个回答提问
hdl coder ram usage and source optimizaion
Dear all, I am using hdl coder and modelling current and speed PI with space vector PWM and SPI blocks. When I go to vivado, I ...
5 years 前 | 1 个回答 | 0
1
个回答提问
hdl coder model checker output latetency and ulp error warning
Hi, I am trying to generate motor speed controller in FPGA. I have completed my model and now I am in code generation phase. I...
5 years 前 | 1 个回答 | 0
1
个回答提问
How can I define FPGA pin as data input in simulink model?
Hello Everyone, I am a new FPGA model-based design learner. Thus, finding what I want is still a puzzle for me. I am studying o...
5 years 前 | 0 个回答 | 0
